New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design

by Siddhartha Nath

Institution: University of California – San Diego
Year: 2016
Keywords: Computer science; Machine Learning; Optimization; VLSI CAD
Posted: 02/05/2017
Record ID: 2092745
Full text PDF: http://www.escholarship.org/uc/item/9jn2c085


In today’s leading-edge semiconductor technologies, it is increasingly difficult for ICdesigners to achieve sufficient improvements of performance, power and area metrics in theirnext-generation products. One root cause of this difficulty is the increased margins that are usedin the design process to guardband for (i) variability and aging, as well as (ii) analysis inaccuracies.Currently, these margins incur huge costs to design companies, because the benefits bydeploying the next technology node is only approximately 20% in circuit performance, powerand density. To reduce margins, fast and accurate pathfinding of architecture, technology andconstraints choices are essential. A second root cause is the high cost (and, therefore, limitedsupply) of electronic design automation tool licenses, accompanied by the lack of any systematicmethodology to optimize the use of available tools within long-duration, highly iterative designprocesses. This constrains designers to perform only limited design-space exploration, so as to keep within limits on design infrastructure cost and design turnaround time. This thesis presentsnew techniques to reduce guardbands in optimization loops in the IC design process by using fastand accurate learning-based models. These techniques can be grouped into three main thrusts:(i) productivity through improved design- and implementation-space exploration; (ii) improvedaccuracy of electrical modeling and enablement of auxiliary physical design optimizations; and(iii) design power, energy, management and cost optimizations.In the productivity through improved design- and implementation-space explorationthrust, this thesis presents four applications of learning-based models for accurate predictionof area, power, timing and routability. To enable area and power estimation of Networks-on-Chip routers, so that architecture-level (RTL-level) design-space exploration can be efficientperformed, this thesis presents an open-source tool, ORION3.0, that has been released on theweb.In the improved accuracy of electrical modeling and enablement of auxiliary physicaldesign optimizations thrust, this thesis presents new methodologies to perform high-dimensionallearning-based modeling of delay, transition time and slack in timing paths. A methodology todevelop accurate models of post-routing optimization of signal delays at multiple signoff corners,so as to enable a new optimization of clock skew variation across corners is also described.In the design power, energy, management and cost optimizations thrust, this thesispresents three distinct works that directly benefit leading-edge SoC design companies. The firstwork describes a new analytic three-dimensional placement tool using a new objective functionthat achieves significant wirelength and power reduction relative to two-dimensional implementations.The second work provides two mixed integer-linear programs for optimal multi-project,multi-resource allocation with task precedence and resource co-constraints for IC design managementand cost reduction. The third…