AbstractsComputer Science

Continuous scaling of Si complementary metal-oxide-semiconductor (CMOS) technology requires a boost in carrier injection velocity. With the benefits of strained Si having been exhausted, n-channel I-V quantum-well field effect transistors (QW-FETs) show promising potential as a post-Si CMOS logic technology. To implement complementary circuits, achieving a high-performance p-channel III-V transistor remains one of the grand challenges. The key problem is the low hole mobility in these materials. In this thesis, we investigate a solution to this problem by exploring uniaxial strain as a means to improve hole mobility in III-V quantum-well structures. We have fabricated Hall structures and QW-FETs on several III-V heterostructures. The channels of these heterostructures include n-channel Ino.15Gao.85As, p-channel GaAs, Ino.2 4Gao.76As and Ino.41Gao.59Sb. We applied uniaxial strain to these devices by bending the I-V chips using a mechanical apparatus. Characteristics of these devices were measured while uniaxial strain was externally applied. Significant hole mobility enhancements were observed under uniaxial compressive stress parallel to the transport direction. Our analysis showed that strain-induced valence band deformation is the dominant mechanism. Nevertheless, two other strain effects were found relevant for QWFET operations: Schottky barrier height change and the piezoelectric effect. Threshold voltage (VT) and gate capacitance (CG) of the QW-FETs were found to be changed by these two effects. For the first time, the piezoresistance coefficients for the three pchannel QWs were determined. A significant finding was that the combination of uniaxial strain with epitaxial biaxial strain appears to enhance the hole mobility in a superlinear way. With high piezoresistance coefficients and high hole mobility, InGaSb appears promising for high-performance p-channel QW-FETs for logic applications. We also developed a device architecture for p-channel InGaAs FETs that incorporates uniaxial strain through a self-aligned dielectric stressor. For the first time, we demonstrated substantial enhancements in the transport characteristics of p-channel InGaAs FETs through the combination of compressive uniaxial strain and compressive epitaxially grown biaxial strain. Strain enhances both the intrinsic transconductance as well as the access resistances. The fabricated structure exhibits promising gate-length scalability and compatibility with self-aligned source/drain metal contacts. Our proposed device architecture holds promise to implement high-performance p-channel III-V FETs for future CMOS logic applications.