Characterization and Modeling of Non-Volatile SONOSSemiconductor Memories with Gridded Capacitors

by Christopher John Barthol

Institution: The Ohio State University
Department: Electrical and Computer Engineering
Degree: PhD
Year: 2015
Keywords: Electrical Engineering; Physics; Gridded Capacitor, Non-Volatile Semiconductor Memory, SONOS
Record ID: 2059743
Full text PDF: http://rave.ohiolink.edu/etdc/view?acc_num=osu1418813120


The demand for high-capacity, low-power memory is increasing rapidly as modernportable electronic devices boost performance while decreasing in size. Due to its many advantages over traditional floating gate memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type semiconductor memories and their various derivatives are the next step in the evolution of Non-Volatile Semiconductor Memory (NVSM) technology. As the SONOS cell size is decreased the gate stack has reached its limitations with silicon oxide used as the defacto oxide for both the blocking and tunneling layers. High K materials, which improve the electrical characteristics while maintaining a thickblocking or cap layer, have started to replace silicon dioxide. The change from asilicon dioxide that has seen over 60 years of development to new materials requiresa rapid turnaround in the fabrication of devices as well as quick characterization ofthe gate stack.We have fabricated gridded Metal-Aluminum Oxide-Nitride-Silicon Oxide-Silicon(MANOS) capacitors. The gridded capacitor structure allow carrier types other thanwhat is originally present in the substrate. This structure is easier to fabricate whilestill allowing all characterization tests, such as speed write/erase and endurance tests, to be performed. This technique does not require ohmic contacts to the grid lines reducing the fabrication process. Two wafer sets have been created. One has analuminum oxide block layer while the other has a hafnium/aluminum oxide blend.The capacitors have been fabricated on <100> p-type silicon wafers with a resistivityof 20 O - cm. A grid structure with line widths of 5µm and line spacing ranging form30µm to 300µm is defined and doped with phosphorous. The gate stacks consist of ahigh quality 2.4nm SiO2 tunnel oxide layer thermally grown in a triple-wall oxidationfurnace, a 7.7nm silicon-rich nitride deposited by LPCVD, and the two sets of clockingoxides deposited by atomic layer deposition (ALD).Various fundamental and dynamic electric characterization techniques such asCapacitance-Voltage, Linear Voltage Ramp, Speed Write/Erase, and Retention measurements have been completed on the gridded capacitor structure. The nuances of each test is described in detail. A flatband voltage tracking system has been created to aid in these measurements. We also discuss a set of simulation programs for charge trap non-volatile memories. The programs show excellent agreement with both full transistors and the gridded capacitor structure.We also present a method to extract carrier mobility with the two terminal gridded capacitor structure where the silicon substrate is implanted with a grid structure of the opposite carrier type. We can extract the carrier mobility as a function of vertical electric field with a combination of Capacitance-Voltage(C-V) andConductance-Voltage(G-V) measurements. In addition, the structure eliminates theneed for source/drain contacts, which lends itself well to material systems where lowresistance, source/drain contacts are difficult to implement and reduce…