AbstractsComputer Science

Clock distribution networks consume a significant portion of total chip powerin high-performance designs. Of many proposed solutions to this drain, clock resonancehas been shown to be an effective method for dealing with chip power and area issueswith savings of 20% in modern designs as well as a lower number of required clockbuffers. Current resonant solutions come with the limitation of optimal performanceat one particular frequency which may be unsuited for the task at hand. For instance,switching from number crunching at work to a kitchen timer at home. If careful tuningis not made then excess power may be spent instead of saved. This thesis introduces thefirst scheme to produce a clock distribution network with a tunable resonant frequency.Experimental results show the resonant frequency ranges from 1.2GHz to 2.6GHz. Thisis done while saving up to 41% power on the clock distribution network when comparedto the non-resonant distribution.