|Institution:||University of Cincinnati|
|Department:||Engineering : Electrical Engineering|
|Keywords:||page oriented optical memoory; CMOS photodetector and receiver; optical read head; photoreceiver array; photonic VLSI|
|Full text PDF:||http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037304111|
Extremely large capacity is needed in the next decade for the application of optical storage memory. To achieve higher data transfer rates page-oriented optical memories have been suggested as replacements for current bit-serial memories in large-capacity memory systems. Although many research endeavors have been concentrated on the development of page-oriented memory,a practical optical storage system also depends on the demonstration of optical read head technologies that are capable of reading and processing data in page-oriented fashion. This thesis explores the possibility for implementing a device to interface an ultra-high density optical storage media with an existing electronic computing hardware. The page-oriented data read capability of a next generation read-head device is demonstrated using current CMOS technology, which is compatible with other electronic circuitry. The circuit was designed and fabricated using a conventional CMOS process. A CMOS based photodetector, which is an unconventional photonic device, was integrated monolithically onto each individual pixel on the chip, as well as the CMOS photoreceiver circuit and other control units. A 2-D pixel array was presented to realize the page-read mode. Test results verify our design of the high sensitivity photoreceiver circuit and high system throughput of the pixel array structure. The final system implementation is expected to serve as the front-end in a page-oriented optical memory system. In the first part of the thesis, a brief introduction to the motivation and background of this project is given. A literature review is presented with an emphasis placed on the design of high performance photoreceivers. The second part of the thesis describes the design, simulation and analysis of the proposed read-head device. Individual components and the whole system are characterized and simulation results shown. While the final system is designed for implementation in a 0.35µm CMOS technology, fabrication costs limited the project to implementation of a test chip in 1.5µm CMOS technology. Finally, the performance evaluation of the fabricated test chip is presented.