AbstractsEngineering

Arithmetic generators of pseudo-exhaustive test patterns

by Sanjay Gupta




Institution: McGill University
Department: Department of Electrical Engineering.
Degree: M. Eng.
Year: 1995
Keywords: Engineering, Electronics and Electrical.
Record ID: 1671216
Full text PDF: http://digitool.library.mcgill.ca/thesisfile22653.pdf


Abstract

This thesis proposes a novel method for implementing test pattern generators for Built-In Self Test (BIST) that eliminates the area and performance penalties associated with existing schemes. The method utilizes adders which are widely available in data-path architectures used in digital signal processing circuits and general purpose processors. Arithmetic test pattern generators produce test patterns by continuously accumulating a constant value. The generated patterns provide complete state coverage on subspaces of contiguous bits and are thus, excellent sources of pseudo-exhaustive tests. In this thesis, several metrics are developed to evaluate the testing properties of different arithmetic generators. Synthesis techniques for a class of generators that exhaustively cover single size subspaces in an optimal manner are formulated. Other generators that best target various ranges of subspace sizes are identified using an efficient search algorithm. Generators with interleaved output spaces are also evaluated. Detailed tables listing the best generators are provided. The proposed test pattern generation scheme, in conjunction with a previously introduced compaction scheme that uses similar existing hardware, now facilitates a non-intrusive, high quality BIST strategy for high performance data-path architectures. This strategy uses the functionality of existing hardware, is entirely integrated with the circuit under test, and permits at-speed testing, using simple BIST control, with no performance degradation or area overhead.