AbstractsEngineering

This thesis is mainly proposed and discussed the characteristics of novel capacitor-less one-transistor dynamic random access transistor (1T-DRAM) with additional pseudo-neutral body region. Because of the shortcoming of the scaled conventional 1T-DRAM, like reduced charge storage region, complex and non-self-aligned fabrication process, leakage current, self-heating effects, and line disturbance issues etc.. Thus, we propose three kinds of novel 1T-DRAM with additional pseudo-neutral body region and maintain the advantages of the trenched body in the planar device in the following, such as the extra charge storage region without additional area cost, and the separated device operation region and charge storage region for reducing the off-state leakage current and improving the transient characteristics, indicating to improve the critical issues of conventional 1T-DRAM mentioned above. 1. We propose the novel vertical silicon-on-insulator (VSOI)-based 1T-DRAM with trenched body. This proposed device is demonstrated to enhance the kink effect, which ensures the floating body effects, comparing with the conventional device. As for the 1T-DRAM memory characteristics, the proposed device receive a wide programming window and long retention time along with a high-speed â1â and â0â state programming operation. Moreover, the multi-functional behavior allows the device to serve in process-in-memory architecture with highly scalability. 2. We propose a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word/bit line disturbance, which is verified by using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4 F2 and with processes that are fully compatible with conventional CMOS technology. This proposed structure also improves the transient performance with good thermal stability and disturbance immunity. 3. Finally, we propose a new 1T-DRAM with an electron-bridge channel structure. This structure built upon bulk substrate can lower the fabrication cost. The wide underlap region enlarge the charge storage region. Also, this region is isolated by the gate/drain depletion region during the programming and read â1â operations. This allows the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, so that the programming window remains viable at high temperature, while also maintaining 26% of the retention performance when operated at 358 K.