AbstractsBiology & Animal Science
Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL:
| Institution: | Delft University of Technology |
|---|---|
| Department: | |
| Year: | 2014 |
| Keywords: | DTC; TDC; ADPLL; ultra-low power; CMOS |
| Record ID: | 1262233 |
| Full text PDF: | http://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d |
Abstract
