AbstractsEngineering

This thesis proposes carrier based Pulse Width Modulation PWM newlineschemes to enhance the performance of the three phase three level NPC newlineinverters and implementation of the proposed PWM schemes in FPGA The newlineperformances of the inverters considered in this thesis are harmonic newlineperformance neutral point voltage variations and low modulation index newlineoperation The harmonic performance of the inverter output can be improved newlineusing suitable PWM control technique Optimal harmonic profile is obtained newlineby centering the middle space vectors in a switching cycle If the expression of newlinecommon mode voltage as calculated for two level inverters is directly applied newlineto multi level inverters the middle vectors may not be centered So the newlineharmonic performance is poor Therefore to improve the harmonic newlineperformance there is a need to calculate the amount of common mode newlineinjection required to center the middle space vectors in a switching cycle The newlineamount of common mode injection depends on the magnitude of the reference newlinevectors The common mode voltage is calculated for various cases and is newlineinjected into the sinusoidal reference signals to produce modified reference newlinesignals The proposed Variable Common Mode Injection Pulse Width newlineModulation VCMIPWM uses modified reference signals Due to this the newlinelinear range operation of inverter is increased and harmonic performance is newlineimproved newline newline%%%reference p132-145.