AbstractsComputer Science

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed memory and I O interfaces in a newlinesingle System on Chip SoC In SoC shared bus based communication newlinearchitecture is used to interconnect the IP blocks However the performance newlineof the bus based communication architecture deteriorates with increased newlinenumber of IP blocks newlineNetworks on Chip NoC has emerged as a feasible solution to newlineovercome the communication problem in the SoC NoC brings the concept of newlinepacket switched network on to the chip In NoC I O blocks are connected newlinethrough routers Standard topologies like Mesh Ring Star and Binary tree are newlinemainly used to interconnect routers and IP blocks Standard topologies are newlinesuitable for NoCs that are reusable for many applications But for newlineApplication Specific NoC ASNoC such standard topologies would lead to newlinepoor performance such as increased area power consumption and latency newlinethereby limiting the use of standard topologies for ASNoC Hence for newlineASNoC tailor made custom topology has to be designed to increase the newlinePerformance The custom topology utilizes fewer resources like routers and newlineinterconnection links that lead to less area and power consumption newline newline%%%reference p158-170.