Nano-scale multi - gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics

by Nikolaos Fasarakis

Institution: Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)
Year: 2014
Keywords: FinFET πολλαπλών πυλών; Ηλεκτρικός χαρακτηρισμός; Συμπαγή μοντέλα; Τεχνική εξαγωγής παραμέτρων; Κατασκευαστική μεταβλητότητα; Multi-Gate FinFET; Electrical characterization; Compact models; Parameter extraction technique; Variability
Record ID: 1153125
Full text PDF: http://hdl.handle.net/10442/hedi/35362


Fundamental goal of this dissertation is to develop compact models for the drain current and trans-capacitances of nano-scale multi-gate (MG) MOSFETs valid in all regions of operation. These models should be suitable for adaptation in modern simulating environments, allowing the design of high performance nano-scale CMOS circuits. Starting with the lightly doped symmetrical double-gate (DG) MOSFET, analytical models are derived for the threshold voltage, the sub-threshold slope, and the DIBL. These parameters are used for the development of a compact charge-based drain current model, continuous in all regions of operation, which includes the short-channel effects, the channel length modulation, the mobility degradation, the saturation velocity and the series resistance effects. Following the same procedure as for DG FinFETs an analytical compact drain current model is developed for triple-gate (TG) FinFETs with rectangular cross-section. Based on the unified expressions for the drain current and the inversion sheet charge density of TG FinFET, a charge-based compact capacitance model is proposed describing the capacitance – voltage characteristics in all regions of operation. A new Y-based methodology is developed for extracting the electrical parameters of modern nano-scale DG and TG FinFETs. Using the already developed drain current equation in the linear region, which involves the LambertW function of the charge at the source, the nonlinear Y-function in these devices is reduced to the linear one of a traditional long-channel MOSFET. The derived new Y-function can be readily applied and evaluate all electrical parameters in a traditional fashion, since all related curves are now linear and easily extrapolated. The proposed methodology for extracting the electrical parameters is verified in both simulated and experimental nano-scale FinFETs, demonstrating its simplicity and good accuracy. Hence, the drain current compact model is implemented for the development of analytical model for the gate current of TG FinFETs, as well as, to evaluate the manufacturing variability and to predict the flicker noise in these devices. The variability model enables the decomposition of the different variability sources, while the flicker noise model captures the carrier number fluctuations with correlated mobility fluctuations effects to accurately model both the geometry and bias dependence of flicker noise. The variability and flicker noise models can be used for circuit simulation tools, as well as a guide for analog designers. The analytical drain current model is simplified to make suitable for digital circuit simulations. An accurate ultra-compact model is proposed, for the description of nano-scale FinFETs, which needs only five physics-based fitting parameters and which is 22 times faster in CPU time, compared to the analytical. Finally, following the analysis of DG MOSFETs, analytical compact model is derived for the drain current and trans-capacitances of nano-scale cylindrical surrounding-gate MOSFETs, using equivalent…