|Institution:||University of New South Wales|
|Department:||Computer Science & Engineering|
|Keywords:||Low power design; Multi-threaded processor; Low enengy design|
|Full text PDF:||http://handle.unsw.edu.au/1959.4/52852|
Multi-threaded processor design enables high performance of a single processor core by transferring the thread-level parallelism to the parallel processing at the instruction level. The design approach increases instruction-level parallelism by mostly re-using existing resources, hence it is cost effective. Most multi-threaded processor designs are mainly implemented at the operating system level and aimed for high system throughput. The performance gain is based on the availability of sufficient number of independent threads, which is often possible for high-end computer systems. The performance improvement and resource re-use in the multi-threaded processor design also offer the potential for energy efficiency, which becomes increasingly important to computing systems, especially to embedded systems. For embedded systems, the requirements for performance, low power/energy consumption are getting even more stringent and have been a challenging topic for the past decade in the embedded systems design area. How to effectively reduce the energy consumption of the multi-threaded processor achieving high performance at the same time for given applications is the key question we want to answer in this research project. In this thesis, we present estimation models for fast evaluation of the performance and energy of different multi-threaded processor designs, where the number of threads targeted for parallel processing and the thread switching methods used are different. We show that the values from the estimation models are consistent with the results produced by the commercial design tools. By the estimation models, large design space can be effectively explored for an optimal design with both low energy consumption and high throughput. To further improve the energy efficiency, we propose to customize the processor design for give applications. We investigate the customization techniques to reduce the register file, a key component in the processor and that can go huge when the thread number in the processor design increases. We have implemented our designs with the commercial hardware design tools for a set of applications. Our simulation results show that about 2 times performance improvement and 34% energy savings can be achieved with our design approaches when compared to the design of single thread processor.